Before choosing an HDI PCB layer count, calculate which gaps can carry a trace, then prove how the required nets reach those gaps. A routing-channel count is a useful rejection test for an impossible fanout. It is not proof that a complete board will route.
This worked review extends the BGA escape-routing guide with a geometric screen and a capacity ledger. All dimensions below are hypothetical and must be replaced with the package supplier’s land pattern and your fabricator’s approved rules.
Define the copper obstacles, not just the ball pitch
Pitch describes the distance between neighboring pad centers. The usable corridor depends on the copper pad diameters and the clearance required on each side of a trace. On an inner layer, the obstacles may instead be via lands or plane openings. Build a separate model for each layer rather than reusing the top-layer pad diameter everywhere.
For two equal circular pads on the same row, let P be center-to-center pitch, D be copper pad diameter, W be trace width, and C be minimum edge clearance. For straight, parallel traces passing through the narrowest gap, n traces need:
nW + (n + 1)C ≤ P − D
There are n trace widths, n−1 spaces between traces, and two clearances to the adjacent pads. Under these simplified assumptions, the maximum nonnegative integer count is floor((P−D−C)/(W+C)). Check the inequality directly after rounding. It describes a local cross-section only; bends, via access and other conductors can still make the route impossible.
Run a small sensitivity study
| Illustrative case | P / D / W / C, mm | Gap P−D | Local result |
|---|---|---|---|
| A | 0.50 / 0.25 / 0.075 / 0.075 | 0.25 mm | One trace needs 0.225 mm; two need 0.375 mm. |
| B | 0.50 / 0.30 / 0.075 / 0.075 | 0.20 mm | Even one trace does not fit. |
| C | 0.50 / 0.25 / 0.050 / 0.050 | 0.25 mm | Two traces need exactly 0.250 mm. |
Case B demonstrates why pitch alone is insufficient. Case C is a boundary result with no additional geometric margin in this model; it is not permission to release a design at an unapproved process limit. Use the clearance definition and tolerances agreed with the manufacturer. Do not independently shrink a component land pattern to make the arithmetic work.
A differential pair needs its own geometry. Replace the repeated W and C terms with the selected pair widths, intra-pair spacing and clearances to surrounding copper. A pair that fits between pads is not automatically at its required impedance. Keep the short escape geometry and the main transmission-line geometry as separate, documented constraints.
Count demand by net and destination
Export the pin map into a review table. Mark used signals, power, ground, unused balls and pins with special connection rules. Do not count an unused I/O as an escape demand merely because its pad exists, and do not remove a required power or reference connection to improve the result.
Then group the used signals by destination and routing constraints. A memory bus heading toward the right edge cannot automatically use spare exits on the left without introducing crossings and extra length. Work quadrant by quadrant, starting with the most constrained interface. The total number of open gaps around the package can hide a severe local bottleneck.
Texas Instruments’ AM62Px escape guidelines, revision B provide a useful counterexample to pitch-only reasoning: that package uses dedicated via channels, and its illustrated board uses through-hole vias rather than HDI. This is a package-specific arrangement, not a general rule for every BGA of similar pitch.
Build a layer-access ledger
For each candidate routing layer, record the via path that reaches it and the obstacles left by that path. A signal layer with no legal transition from the required ball provides no useful escape capacity. Include the landing pads of staggered transitions and the space needed to move between them.
Eurocircuits’ HDI fanout examples illustrate how pin arrangement, used pins and supported via geometry affect routability. Their staggered-microvia examples describe their stated process; another factory’s permissible spans and lands may differ.
A practical ledger has columns for layer, accessible nets, exits used, exits blocked, remaining demand and unresolved assumptions. Count each route only once. Mark shared corridors explicitly so two interfaces do not both claim the same space. Keep the nearest reference plane and its return-path requirements visible alongside the signal count.
Prove the bottleneck before completing the board
Route one representative congested region using real footprints, decoupling placement and keepouts. Continue beyond the BGA perimeter far enough to show that the escaped nets can enter the main routing channels. Check power access and inspect plane perforation from the via field. Passing a local trace-gap calculation does not protect a return path.
If the study fails, identify the reason before adding layers: an inaccessible layer, a blocked destination corridor, an oversized transition land or conflicting component placement call for different remedies. A placement change can recover useful channels without another build-up step. Use the HDI component-placement guide when escape capacity and surrounding components compete for the same area.
What to send for fabrication review
- The exact package land pattern and used-pin map.
- The proposed layer functions and every via span.
- The W, C and copper-land dimensions used in the channel screen.
- A routed bottleneck example with remaining unrouted nets identified.
- Reference-plane, impedance and assembly questions that remain open.
Record these inputs in the design checklist and retain the reviewed revision. Explore the HDI design library for the next decisions, or request a construction review with the study attached. The useful result is a defensible candidate stackup, not a layer count inferred from pitch alone.
Sources reviewed 9 October 2026. Calculated examples are illustrative local geometry, not validated fabrication limits.