An HDI escape can solve package congestion while leaving a poor USB 3 channel at the connector or layer transition. Review the complete path as a sequence of launches, traces, components and transitions. A clean trace-length report alone does not approve that channel.
This guide provides a layout-review worksheet for an illustrative USB 3 design. It does not claim that USB requires HDI, or that a particular commercial product uses it. The device documentation, connector model and released stackup must supply the project’s actual limits.
Start with a route inventory
Write down the controller, intended USB mode, connector part number and every device in the signal path. Identify transmit and receive pairs separately. Include a mux, protection device, coupling component or redriver wherever the schematic actually requires it. Do not add one simply because it appears in a generic reference design.
Give each channel segment a name and associate it with its routing layer, reference plane and physical endpoints. Then add the package escape and connector launch as explicit segments. This makes a hidden layer change or component footprint visible before the reviewer begins checking dimensions. Keep the schematic and layout revisions together so the inventory is not obsolete when routing changes.
Use vendor guidance within its stated scope
Texas Instruments’ SLLA414A layout application note discusses connector-pin stubs, via discontinuities and differential-pair symmetry. Its connector examples distinguish through-hole and surface-mount receptacles because the appropriate connection layer affects the unused conductive path. Apply that reasoning to the actual connector drawing rather than copying a layer choice without checking the package orientation.
TI’s separate USB layout lesson emphasizes matching within each pair and preserving return continuity through symmetric transitions. Neither resource is a qualification report for the board you are designing. Use the selected controller and connector requirements to define acceptance, and investigate any conflict between generic guidance and device-specific instructions.
Audit the connector launch in cross-section
A top-view footprint can conceal the part of a pin or plated hole that extends beyond the signal connection. Draw the connection in cross-section with the connector seating side, relevant copper layers and unused conductor identified. Ask whether the selected route enters the pin at the intended location and whether the proposed geometry is represented in the available model.
For a surface-mount connector, inspect the path from contact land to the main pair. The pad-to-trace change and nearby reference geometry belong to the launch. For a through-hole connector, distinguish the electrically used pin length from the remaining branch. HDI microvias elsewhere on the board do not remove an unrelated connector stub.
Record what you know and what remains unmodeled. If a connector vendor provides a recommended launch, retain the document revision and identify every departure. Avoid calling a footprint “validated” when only its mechanical dimensions have been checked. The electrical and assembly reviews are related but answer different questions.
Create a transition ledger
| Location | Evidence to inspect | Question to close |
|---|---|---|
| Package escape | Both pair members, lands and via spans | Do they use comparable electrical structures? |
| Layer change | Before/after references and ground connections | How does return current reach the new reference? |
| Inline component | Footprint, pad geometry and placement | Is the actual mounted structure represented? |
| Connector launch | Pin cross-section and entry layer | Is an unused conductive branch present? |
Number every transition on a layout screenshot and use the same numbers in the ledger. A reviewer should be able to move from a worksheet row to the exact geometry without searching the board. Include the ground connectivity rather than showing only the two signal conductors. The return-path guide explains the broader reference-plane review.
For a compound HDI transition, list each span individually. Two paths can have the same number of drawn via symbols yet differ in span, landing geometry or reference environment. Conversely, a simple via count cannot determine the loss of a transition. Record the actual structures and assess their electrical behavior with the project’s chosen analysis method.
Compare two routing candidates without changing the question
Consider a hypothetical board where a dense package exits near one edge and the USB connector is on another. Candidate A keeps most of the route on an outside layer but takes a longer path around components. Candidate B uses an internal routing region and adds transitions. Neither candidate wins merely because it is shorter or uses fewer vias.
Hold the connector, endpoint models and acceptance criteria constant. For each candidate, document trace segments, transition structures, reference continuity and any excluded geometry. Compare the resulting channel assessment and retain the modeling assumptions. If one model excludes the connector launch while the other includes it, the results are not a fair comparison.
Use the controlled-impedance guide to organize the stack and fabrication inputs. An impedance value for a uniform trace section does not automatically describe the entire route. Keep the launch and transition questions open until their evidence is available, rather than allowing a calculator result for the straight section to close them.
Plan verification before freezing the layout
Identify what analysis and physical measurements will be used to accept the channel. Record fixtures, reference planes and any de-embedding assumptions when measurements are planned. Decide which hardware configurations and connector orientations must be checked. A successful connection in one convenient setup is useful debug information, but it does not replace the project’s full verification plan.
If a design revision changes the connector, stackup or protection footprint, reopen the affected ledger rows. Preserve the earlier results with their original geometry instead of silently reusing them for the new revision. This prevents a model that once described the board correctly from becoming misleading evidence later.
Release checklist
- Document the exact USB mode, endpoints and component path.
- Inspect the package escape and connector launch in the real stack.
- Record each signal and return-path transition.
- Reconcile the layout with the geometry included in analysis.
- Agree verification criteria and retain revision-linked results.
Use the signal-routing checklist tool to organize open questions and the signal-integrity library for related topics. For a fabrication review, provide the transition ledger alongside the stackup and design files. The tool is a planning aid, not a USB compliance test or field solver.
Sources reviewed 9 October 2026. The routing candidates are illustrative. No universal trace length, via count or pass/fail channel limit is asserted.