Balance interfaces and power domains. Evaluate 1+10+1 or 2+8+2 as candidate notation, then verify the actual escape and plane allocation.
What to consider
Twelve layers are useful when interface groups and power distribution require several distinct copper functions. Extra layers do not by themselves provide access through a tightly packed BGA field.
Conceptual layer allocation
Compare 1+10+1 or 2+8+2. This illustration assigns copper functions only; it does not define dielectric thickness, impedance or an approved via structure.
| Build-up per side | Core copper layers | Total copper layers |
|---|---|---|
| 1 | 10 | 12 |
| 2 | 8 | 12 |
| 3 | 6 | 12 |
A practical review example
For a processor plus multiple memory devices, map each interface to candidate layers and mark every reference change. Compare the routing plan against the actual core-via land size.
Checks before release
- Allocate signal, ground and power copper before counting routing capacity.
- Agree pressed dielectric values and finished thickness.
- Define every laser and mechanical via span.
Connect this decision to fabrication
Use the stackup planner to organize the initial discussion. Keep proposed values separate from the approved drawing and document the effect of any change on the rest of the construction.
- Give every signal layer a defined return-path strategy.
- Review material and copper balance about the board center.
- Specify every via span and the factory-approved lamination sequence.
Technical references
HDI construction types and definitionsFabrication design guidelinesReferences checked 2 October 2026. Manufacturer data describes its stated construction and is not an HDIPCB.org manufacturing commitment.