Make room for controlled-impedance routing. Evaluate 1+8+1 or 2+6+2 as candidate notation, then verify the actual escape and plane allocation.
What to consider
Ten layers offer more room to dedicate ground references while separating dense component escape from longer channels. Review the distance between each routing layer and its reference instead of assuming all inner layers are equivalent.
Conceptual layer allocation
Compare 1+8+1 or 2+6+2. This illustration assigns copper functions only; it does not define dielectric thickness, impedance or an approved via structure.
| Build-up per side | Core copper layers | Total copper layers |
|---|---|---|
| 1 | 8 | 10 |
| 2 | 6 | 10 |
| 3 | 4 | 10 |
A practical review example
A processor board may reserve outer build-up layers for breakout and move longer channels to referenced core routing layers. Define the transition from the fine-pitch region to the core.
Checks before release
- Allocate signal, ground and power copper before counting routing capacity.
- Agree pressed dielectric values and finished thickness.
- Define every laser and mechanical via span.
Connect this decision to fabrication
Use the stackup planner to organize the initial discussion. Keep proposed values separate from the approved drawing and document the effect of any change on the rest of the construction.
- Give every signal layer a defined return-path strategy.
- Review material and copper balance about the board center.
- Specify every via span and the factory-approved lamination sequence.
Technical references
HDI construction types and definitionsFabrication design guidelinesReferences checked 2 October 2026. Manufacturer data describes its stated construction and is not an HDIPCB.org manufacturing commitment.