A compact escape layer on each face. Evaluate 1+2+1 as candidate notation, then verify the actual escape and plane allocation.
What to consider
With only four copper layers, routing, power distribution and return paths compete for the same space. Reserve the inner copper deliberately; do not turn the nearest reference plane into an unplanned breakout layer.
Conceptual layer allocation
Compare 1+2+1. This illustration assigns copper functions only; it does not define dielectric thickness, impedance or an approved via structure.
| Build-up per side | Core copper layers | Total copper layers |
|---|---|---|
| 1 | 2 | 4 |
A practical review example
A low-I/O sensor module can use outer signal layers referenced to inner ground regions. If power distribution fragments those regions, increasing layer count may be more useful than forcing extra escapes.
Checks before release
- Allocate signal, ground and power copper before counting routing capacity.
- Agree pressed dielectric values and finished thickness.
- Define every laser and mechanical via span.
Connect this decision to fabrication
Use the stackup planner to organize the initial discussion. Keep proposed values separate from the approved drawing and document the effect of any change on the rest of the construction.
- Give every signal layer a defined return-path strategy.
- Review material and copper balance about the board center.
- Specify every via span and the factory-approved lamination sequence.
Technical references
HDI construction types and definitionsFabrication design guidelinesReferences checked 2 October 2026. Manufacturer data describes its stated construction and is not an HDIPCB.org manufacturing commitment.